Multi-phase layout structure and method

ABSTRACT

The present invention provides a multi-phase layout structure and method. The layout structure comprises: a first layout layer; a second layout layer substantially parallel to the first layout layer; a plurality of traces, each transmitting a signal, and the plurality of signals having a phase difference between each other; wherein a horizontal coupling capacitance is provided between two neighboring traces configured on the same layer of the first layout layer and the second layout layer, a vertical coupling capacitance is provided between two neighboring traces configured on different layers of the first layout layer and the second layout layer, and the plurality of traces have substantially the same total coupling capacitance wherein the total coupling capacitance is defined by the horizontal coupling capacitance and the vertical coupling capacitance.

CROSS-REFERENCES TO RELATED APPLICATIONS

This non-provisional application claims priority under 35 U.S.C. §119(a) on Patent Application No(s). 96119948 filed in Taiwan, R.O.C. onJun. 4, 2007, the entire contents of which are hereby incorporated byreference.

TECHNICAL FIELD

The present invention relates to a layout structure and method, andparticularly to a multi-phase layout structure and method.

BACKGROUND OF THE INVENTION

In the conventional technology, multi-phase signal layout causes delaysbecause of the length of the signal line. Although wafer processing hasnot entered the sub-micron level, great attention should be paid tolayout arrangement in order to avoid serious resistance/capacitanceeffect, and particularly to avoid excessively long traces which maycause excessive system delay.

In the conventional trace arrangement, the layout proceeds withoutviolating the design rules from the fab. However, in the actual circuitlayout, the traces exhibit coupling capacitance in between, resulting inundesired effects more serious than expected. Serious interference mayoccur if the traces of the analog circuit are arranged near the digitalcircuit. This is especially the case for an analog circuit, which ismore sensitive.

In addition to the effect caused by coupling capacitance, multi-phasedelay time also causes other problems. FIG. 1A is a schematic viewshowing a layout of multi-phase signal traces in the prior art. Althoughthe signal traces are of equal length, the loading viewed from onesignal trace (such as coupling capacitance), may not be identical tothat from another signal trace, so that the delay time from the input tothe output (td0, td1 . . . ), for the signal on each signal trace mayvary (td0≠td1≠ . . . ). The varied delay time between phases mayinfluence, for example, the characteristics and performance of acircuit. Therefore, another layout method for multi-phase signal tracehas been proposed in the prior art, as shown in FIG. 1B; wherein agrounding trace or a grounding potential is provided between each twosignal traces in the tracing arrangement. The signal of each phase thushas an equal delay time from input to output. However, the layout methodin FIG. 1B has other defects. For example, a larger layout area isneeded.

The difficulty of how to solve the effect caused by coupling capacitancein the layout method thus becomes an urgent problem requiring solution.

SUMMARY OF INVENTION

To this end, the present invention discloses a layout structure fortransmitting multi-phase signals, which can effectively eliminate theeffect caused by the delay time between multi-phase signals. Byemploying a geometrically symmetric mechanism or electrically symmetricmechanism, the present invention ensures the coupling capacitancesbetween phases match each other.

The present invention provides a layout structure for transmittingmulti-phase signals, which comprises: a first layout layer; a secondlayout layer substantially parallel to the first layout layer; aplurality of traces, each transmitting a signal, and the plurality ofsignals having a phase difference between each other; wherein ahorizontal coupling capacitance is provided between two neighboringtraces configured on the same layer of the first layout layer and thesecond layout layer, a vertical coupling capacitance is provided betweentwo neighboring traces configured on different layers of the firstlayout layer and the second layout layer, and the plurality of traceshave substantially the same total coupling capacitance wherein the totalcoupling capacitance is defined by the horizontal coupling capacitanceand the vertical coupling capacitance.

The present invention also provides another layout method, whichincludes the following steps: providing a first layout layer and asecond layout layer, where the first layout layer and the second layoutlayer are substantially parallel to each other; forming a plurality ofsignal traces, in which a horizontal coupling capacitance is providedbetween two neighboring traces configured on the same layer of the firstlayout layer and the second layout layer, a vertical couplingcapacitance is provided between two neighboring traces configured ondifferent layers of the first layout layer and the second layout layer,and the plurality of traces have substantially the same total couplingcapacitance wherein the total coupling capacitance is defined by thehorizontal coupling capacitance and the vertical coupling capacitance.

With reference to the drawings appended herewith, the preferredembodiments and the benefits of the present invention will be furtherdescribed as follows.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A is a diagram showing a first type of conventional multi-phase,high frequency circuit layout;

FIG. 1B is a diagram showing a second type of conventional multi-phasehigh frequency circuit layout;

FIG. 2A is a principle exposition diagram (1);

FIG. 2B is a principle exposition diagram (2);

FIG. 2C is a schematic view of a first embodiment of the presentinvention (1);

FIG. 2D is a schematic view of the first embodiment of the presentinvention (2);

FIG. 2E is a top view of the first embodiment of the present invention;

FIG. 3A is a first schematic view of a second embodiment of the presentinvention;

FIG. 3B is a second schematic view of the second embodiment of thepresent invention;

FIG. 4A is a schematic view of a third embodiment of the presentinvention;

FIG. 4B is a top view of the third embodiment of the present invention;and,

FIG. 5 is a schematic view of a fourth embodiment of the presentinvention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Before the description of the present invention, please first refer toFIG. 2A, which is a principle exposition diagram (1). In FIG. 2A, tracea is used to transmit Vx voltage signal, and trace b is used to transmit−Vx voltage signal, that is, the signals transmitted by trace a andtrace b will have a phase difference of 180 degree. As deduced using theformula below, the left-hand circuit in FIG. 2A is equivalent to theright-hand circuit.

$\begin{matrix}{{C = \frac{q}{V}};} & (1) \\{{i = \frac{q}{t}};} & (2) \\{{i = {{Cf} \times \frac{V}{t}}};} & (3)\end{matrix}$

$\begin{matrix}{{\frac{q}{t} = {{Cf} \times \frac{V}{t}}};} & (4)\end{matrix}$

By substituting (2) into (3):

The voltage variance in unit time is Vx−(−Vx)=2Vx, so (4) becomes:

q=Cf×2V . . . (5), then substituting (5) into (1): C=2Cf.

Next, please refer to FIG. 2B, which is a principle exposition diagram(2). As shown in the figure, the a is transmitting a sinusoidal signalwith phase angle sin(w₀t−90°), and the b is transmitting a sinusoidalsignal with a phase angle sin w₀t, and trace c is transmitting asinusoidal signal with phase angle sin(w₀t+90°); wherein, the signalstransmitted by trace a and trace c the phrase difference between the twotraces is 180 degrees. From the result in FIG. 2A, it can be seen thatwhen the coupling capacitance between trace a and trace b and thecoupling capacitance between trace b and trace c are matched with eachother, the left-hand circuit in FIG. 2B is equivalent to the right-handcircuit. Thus, when the capacitances between traces are matched witheach other, the disadvantages caused by the capacitance can be construedas removed.

Please refer to FIG. 2C, which is a schematic view of a first embodimentof the present invention (1). The layout structure for multi-phasesignal of the first embodiment comprises: a first layout layer 10, asecond layout layer 12, a first trace 30, a second trace 40, a thirdtrace 50 and a fourth trace 60. The first trace 30, the second trace 40,the third trace 50 and the fourth trace 60 are used to respectivelytransmit four multi-phase signals. The phases of the four multi-phasesignals are 0 degrees, 90 degrees, 180 degrees, and 270 degrees. Forconvenience of description, please refer to the first half of FIG. 2C,which is FIG. 2D.

As shown in FIG. 2D, the first layout layer 10 and the second layoutlayer 12 are in parallel, and the first layout layer 10 has a firstlocation 20 and a fourth location 26, and the second layout layer 20 hasa second location 22 and a third location 24.

There is a coupling capacitance between two neighboring traces. Forexample, a horizontal coupling capacitance Ch is provided between twoneighboring traces configured on the same layer of the first layoutlayer 10 and the second layout layer 12. As shown in FIG. 2D, the firsttrace 30 and the fourth trace 60 have a horizontal coupling capacitanceCh in between, and the second trace 40 and the third trace 50 also havea horizontal coupling capacitance Ch in between. On the other hand, avertical coupling capacitance Cv is provided between two neighboringtraces configured on different layers of the first layout layer and thesecond layout layer. As shown in FIG. 2D, the first trace 30 and thesecond trace 40 have a vertical coupling capacitance Cv in between, andthe fourth trace 60 and the third trace 50 also have a vertical couplingcapacitance in between. As shown in FIG. 2D, the signals transmitted bytwo neighboring traces for each trace the phase difference between thetwo traces is 180 degrees, for example, the two neighboring traces ofthe first trace 30 are the second trace 40 and the fourth trace 60, andthe signals transmitted by the second trace 40 and the fourth trace 60respectively have the phase at 90 degrees and 270 degrees (−90 degrees);and, the two neighboring traces of the second trace 40 are the firsttrace 30 and the third trace 50, and the signals transmitted by thefirst trace 30 and the third trace 50 respectively have the phase at 0degrees and 180 degrees; similarly, the two neighboring traces of thethird trace 50 are the second trace 40 and the fourth trace 60, and thetwo neighboring traces of the fourth trace 60 are the first trace 30 andthe third trace 50. From the principle exposition diagram of FIG. 2B, itcan be seen that the layout structure can eliminate the effect ofcoupling capacitance. Such a layout structure employs a geometricallysymmetrical mechanism to eliminate the effect of coupling capacitance.

Please refer to FIG. 2C again, especially for the first half and thesecond half of FIG. 2C. It can be found that the layout in the secondhalf of FIG. 2C is rotated 90 degrees clockwise from the position in thefirst half of FIG. 2C. Please refer to FIG. 2C. As shown in FIG. 2C, thefirst trace 30 includes a first section 31 and a second section 32, thesecond trace 40 includes a first section 41 and a second section 42, thethird trace 50 includes a first section 51 and a second section 52, andthe fourth trace 60 includes a first section 61 and a second section 62.That is, by rotating the first section of each trace 90 degreesclockwise, the position configured for the second section of each traceis achieved. Herein, without being limited to a 90 degrees clockwiserotation, the same effect is achieved as by rotating 90 degreescounterclockwise. Further, as shown in the figure, the first section ofone of the first trace 50 through to the fourth trace 60 issubstantially overlaid with the first section of another one of theplurality of traces. For example, the first section 31 of the firsttrace is overlaid with the first section 41 of the second trace; and,the first section 61 of the fourth trace is also overlaid with the firstsection 51 of the third trace.

It should be explained firstly that the first section and the secondsection of each trace are connected with each other. In FIG. 2C thefirst section and the second section of each trace are shown separatelyfor convenience. Moreover, the length of the first section may be equalto the length of the second section for each trace.

Please refer to FIG. 2E, which is a top view of FIG. 2C. The top view ofthe layout arrangement of each trace on the first layout layer and thesecond layout layer can be seen clearly. The bolded lines in the figureindicate the traces located on the first layout layer, and the thinlines indicate the traces located on the second layout layer. As shownin the figure, it can be seen clearly that the first section and thesecond section of each trace are connected with each other.

Please refer regularly to FIG. 2C. The first section 61 of the fourthtrace and the first section 31 of the first trace have a horizontalcoupling capacitance Ch in between, and the second section 62 of thefourth trace and the second section 32 of the first trace have avertical coupling capacitance Cv in between, so that the couplingcapacitance between the first trace and the fourth trace is a parallelconnection of the horizontal coupling capacitance Ch and the verticalcoupling capacitance Cv. Similarly, the total coupling capacitancebetween a trace and its neighboring traces (i.e. a parallel connectionof the horizontal coupling capacitance Ch and the vertical couplingcapacitance Cv) is substantially identical for each trace, so as toachieve electrical symmetry. Thus, the electrical characteristics forthe first trace 30, the second trace 40, the third trace 50 and thefourth trace 60 defined by the horizontal coupling capacitance Ch andthe vertical coupling capacitance Cv are substantially identical.

It can be deduced from the above that the total coupling capacitancebetween a trace and its neighboring traces is the sum of the horizontalcoupling capacitance Ch and the vertical coupling capacitance Cvconnected in parallel, that is, substantially equal to Ch+Cv.

Please refer to FIG. 3A, which is a first schematic view of a secondembodiment of the present invention. In the embodiment, similarly, eachtrace includes two sections. The difference between FIG. 3A and FIG. 2Dis that in the second embodiment the first section 41 and the secondsection 42 of the second trace 40 are configured at the same locationi.e. the second location 22. Similarly, the first section 61 and thesecond section 62 of the fourth trace 60 are configured at the samelocation, i.e. the second location 26. In the tracing, the first sectionand the second section of the first trace 30 and the third trace 50 areconfigured at different locations. As shown in the figure, the layoutdesign similarly allows the total coupling capacitance between a traceand its neighboring traces to be the sum of the horizontal couplingcapacitance Ch plus the vertical coupling capacitance Cv, therefore, thetotal coupling capacitances between traces are matched with each other.

Similarly, the first section 31 and the second section 32 of the firsttrace 30, and the first section 51 and the second section 52 of thethird trace 50 can be also configured at the same locations, i.e. thefirst location 20 and the third location 24, respectively. In contrast,the first sections of the second trace 40 and the fourth trace 60 arerespectively configured at the second location 22 and the fourthlocation 26, the second sections of the second trace 40 and the fourthtrace 60 interchange their positions, are respectively configured at thefourth location 26 and the second location 22, as shown in FIG. 3B.

FIG. 4A is a schematic view of the preferred of the present invention,i.e. the third embodiment. In the third embodiment, the first trace 30includes a first section 31 to a fourth section 34; the second trace 40includes a first section 41 to a fourth section 44; the third trace 50includes a first section 51 to a fourth section 54; and, the fourthtrace 60 includes a first section 61 to a fourth section 64. The firstsections of first trace 30 through to fourth trace 60 are respectivelyconfigured at the first location 20 to the fourth location 26; next,rotating the second section of each trace 90 degrees; and, furtherrotating the third section of each trace 90 degrees in the samedirection; finally, further rotating the fourth section of each trace 90degrees in the same direction. With the above-mentioned configuration,the total coupling capacitances between traces will all be as follows:the first horizontal coupling capacitance Ch1 in parallel connectionwith the second horizontal coupling capacitance Ch2 in parallelconnection with the first vertical coupling capacitance Cv1 in parallelconnection with the second vertical coupling capacitance Cv2. Thus, thetotal coupling capacitances between traces are matched with each other,and all equal Ch1+Ch2+Cv1+Cv2.

Please refer to FIG. 4B, which is a top view corresponding to FIG. 4A.It can be clearly seen from the top view how the first section to thefourth section of each trace are configured on the first layout layerand the second layout layer, and it can also be clearly seen that thefirst section to the fourth section of each trace are connected witheach other. Moreover, the first section to the fourth section of eachtrace may have an identical length.

The trace layout in the above-mentioned first to third embodiments isgeometrically symmetrical. The term “geometrically symmetrical” meansthat the geometrical shape is completely symmetrical and consistentregardless of the angle from which trace the layout structure is viewed.With a geometrical symmetry, the total coupling capacitances betweenphases are matched with each other for eliminating the effect ofcapacitance and delay time.

Please refer to FIG. 5, which is a schematic view of a fourth embodimentof the present invention. The difference between the fourth embodimentand the above-mentioned embodiment is that the present embodiment willadjust the distance between traces to ensure the total couplingcapacitances between traces match each other.

The fourth embodiment also exemplifies the present invention by usingfour traces, but the number of the traces is not limited to four. Thefirst trace 30 is configured on the first layout layer 10 fortransmitting the first signal. The second trace 40 is configured on thesecond layout layer 12 for transmitting the second signal, and the phasedifference between the second signal and the first signal is 90 degree.The third trace 50 is configured on the second layout layer 12 fortransmitting the third signal, and the phase difference between thethird signal and the second signal is 90 degrees. The fourth trace 60 isconfigured on the first layout layer 10 for transmitting the fourthsignal, and the phase difference between the fourth signal and the thirdsignal is 90 degrees. The signals transmitted by each trace may be ahorizontally synchronized signal.

Two neighboring traces configured in the first layout layer 10 and thesecond layout layer 12 (as shown in the figure, the first trace 30 andthe fourth trace 60, and the second trace 40 and the third trace 50)have a horizontal coupling capacitance Ch in between the two neighboringtraces. On the other hand, two neighboring traces configured ondifferent layers of the first layout layer 10 and the second layoutlayer 12 (as shown in the figure, the first trace 30 and the secondtrace 40, and the fourth trace 60 and the third trace 50) has a verticalcoupling capacitance Cv in between. Because of the existence of thecoupling capacitance between traces, the capacitance value is inverselyproportional to the distance between the two traces. Thus, based on thisproperty, the total coupling capacitance (no matter the horizontalcoupling capacitance Ch or the vertical coupling capacitance Cv) betweentraces for each trace can be matched with each other by adjusting thedistance between traces, that is, the horizontal coupling capacitance Chis substantially equal to the vertical coupling capacitance Cv. Thetrace layout in this embodiment is electrically symmetrical. The term“electrically symmetrical” means that the electrical characteristics areall symmetrical and consistent no matter from which trace the layoutstructure is viewed. The effect of capacitance and delay time is thuseliminated.

Although the technical contents of the present invention have beendisclosed with reference to the embodiments as stated above, theseembodiments are not intended to limit the present invention. Thoseproficient in the relevant fields can make changes and modificationswithout departing from the spirit of the present invention, and thesechanges and modification should be all included in the scope of thepresent invention. Therefore, the protection scope of the presentinvention will be defined by the attached claims.

1. A layout structure, which comprises: a first layout layer; a secondlayout layer, which is substantially parallel to the first layout layer;and, a plurality of traces, each transmitting a signal, and theplurality of signals having a phase difference between each other;wherein two neighboring traces configured on the same layer of the firstlayout layer and the second layout layer have a horizontal couplingcapacitance in between, two neighboring traces configured on differentlayers of the first layout layer and the second layout layer have avertical coupling capacitance in between, and the plurality of traceshave substantially the same total coupling capacitances wherein thetotal coupling capacitance is defined by the horizontal couplingcapacitance and the vertical coupling capacitance.
 2. The layoutstructure of claim 1, wherein the total coupling capacitance is theparallel connection of at least one horizontal coupling capacitance andat least one vertical coupling capacitance.
 3. The layout structure ofclaim 1, wherein the phase differences between the plurality of signalsare substantially 0 degrees, 90 degrees, 180 degrees and 270 degreesrespectively.
 4. The layout structure of claim 1, wherein the phasedifference between the signals transmitted on two neighboring traces foreach trace is substantially 180 degrees.
 5. The layout structure ofclaim 1, wherein each of the traces comprises a first section and asecond section; and the second section in each of the traces is at aposition corresponding to the position of the first section of the sametrace with a clockwise or counterclockwise rotation of 90 degrees. 6.The layout structure of claim 5, wherein the first section and thesecond section are of substantially identical length.
 7. The layoutstructure of claim 1, wherein each of the traces comprises a firstsection, a second section, a third section and a fourth section.
 8. Thelayout structure of claim 7, wherein the first section, the secondsection, the third section and the fourth section are of substantiallyidentical length.
 9. The layout structure of claim 7, wherein the firstsection, the second section, the third section and the fourth sectionare positioned clockwise or counterclockwise.
 10. A layout method, whichcomprises the following steps: providing a first layout layer and asecond layout layer, and the first layout layer and the second layoutlayer are substantially parallel to each other; and, forming a pluralityof signal traces, wherein two neighboring traces configured on the samelayer of the first layout layer and the second layout layer have ahorizontal coupling capacitance in between, two neighboring tracesconfigured on different layers of the first layout layer and the secondlayout layer have a vertical coupling capacitance in between, and theplurality of traces have substantially the same total couplingcapacitances wherein the total coupling capacitance is defined by thehorizontal coupling capacitance and the vertical coupling capacitance.11. The layout method of claim 10, wherein the total couplingcapacitance is a parallel connection of at least one horizontal couplingcapacitance and at least one vertical coupling capacitance.
 12. Thelayout method of claim 10, wherein the phase differences among theplurality of signals are substantially 0 degree, 90 degrees, 180 degreesand 270 degrees, respectively.
 13. The layout method of claim 10,wherein the phase difference between the signals transmitted on twoneighboring traces for each trace is substantially 180 degrees.
 14. Thelayout method of claim 10, wherein each of the traces comprises a firstsection and a second section; and the second section in each of thetraces is at a position corresponding to the position of the firstsection of the same trace with a clockwise or counterclockwise rotationof 90 degrees.
 15. The layout method of claim 14, wherein the firstsection of one of the plurality of signal traces is substantiallyoverlaid with the first section of another of the plurality of signaltraces.
 16. The layout method of claim 14, wherein the first section andthe second section are of substantially identical length.
 17. The layoutmethod of claim 10, wherein each of the traces comprises a firstsection, a second section, a third section and a fourth section.
 18. Thelayout method of claim 17, wherein the first section, the secondsection, the third section and the fourth section are of substantiallyidentical length.
 19. The layout method of claim 17, wherein the firstsection, the second section, the third section and the fourth sectionare positioned clockwise or counterclockwise.